Design of Digital Circuits (Spring 2019)
Design of Digital Circuits, ETH Zürich, Spring 2019
Professor Onur Mutlu (http://people.inf.ethz.ch/omutlu)
Course website (with slides, readings and homeworks):
https://safari.ethz.ch/digitaltechnik/spring2019/doku.php
视频选集
（26/34）
Lecture 1: Introduction and Basics
01:22:29
Lecture 2: Mysteries in Comp Arch
01:30:37
Lecture 3: Introduction to the Labs and FPGAs
01:11:09
Lecture 4: Combinational Logic I
01:30:50
Lecture 5: Combinational Logic II
01:32:11
Lecture 6: Sequential Logic Design
01:27:45
Lecture 7.1: Sequential Logic Design II
21:13
Lecture 7.2: Hardware Description and Verilog
01:09:07
Lecture 8: Timing and Verification
01:34:22
Lecture 9: Von Neumann Model, ISA, LC-3, MIPS
01:29:51
Lecture 10a: Instruction Set Architecture
48:59
Lecture 10b: Assembly Programming
37:47
Lecture 11: Microarchitecture
01:29:50
Lecture 12: Microarchitecture II
01:30:28
Lecture 13: Pipelining
01:29:14
Lecture 14: Pipelining Issues
01:31:24
Lecture 15a: Reorder Buffer
48:28
Lecture 15b: Out-of-Order Execution
44:10
Lecture 16: OoO, DataFlow, Loads/Stores
01:32:48
Lecture 17a: Superscalar Execution
24:44
Lecture 17b: Branch Prediction
01:05:04
Lecture 18: Branch Prediction II
01:32:00
Lecture 19a: VLIW
30:03
Lecture 19b: Systolic Arrays and Beyond
01:04:59
Lecture 20: SIMD Processors
01:34:36
Lecture 21: Graphics Processing Units
01:29:16
Lecture 22a: Memory Organization & Technology
01:01:44
Lecture 22b: Memory Hierarchy and Caches
31:54
Lecture 23: More Caches
01:31:53
Lecture 24a: Multiprocessor Caches
01:09:56
Lecture 24b: Virtual Memory
21:52
Lecture 25: Virtual Memory II
01:35:53
Lecture 26: Epilogue
32:56
Discussion Session I
01:02:11
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