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【计算机结构 Computer Architecture】-台湾清华大学-黄婷婷教授

7.5万
552
2019-05-26 13:19:06
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台湾清华大学
体系结构
孤雁寒窗 发消息
视频选集
（99/99）
L1-1 Transistor, CMOS, Computer Organization
17:55
L1-2 Instruction Set Architecture (ISA)
17:30
L2-1 Computer history
15:26
L2-2 RISC, CISC, Moore's Law
17:46
L2-3 Computer Usage
11:04
L3-1 Level of program code, Components of a Computer
14:59
L3-2 Abstraction, Technology, Performance
13:22
L3-3 Execution time, Relative performance, CPU time
13:19
L3-4 CPU Time example
03:40
L4-1-1 Instruction Count and CPI -1
07:13
L4-1-2 Instruction Count and CPI -2
12:22
L4-2 Performance Summary, Power Trends, Multiprocessors
20:38
L4-3 Measuring and evaluating performance
14:48
L4-4 Cost
19:53
L4-5 Instruction set architecture, Operations of Hardware
14:20
L4-6 Operands and Registers, MIPS Registers
13:25
L5-1 Operation of Hardware, Register Architecture
14:33
L5-2 Memory Operand, Data transfer: Memory to Register
14:18
L5-3 Data transfer: Register to Memory
14:10
L5-4 Memory operands Example
05:50
L6-1 Memory operands, data transfer
14:30
L6-2 Immediate operands
14:35
L6-3 Representing instructions
14:58
L6-4 Representing instructions 2
04:43
L6-5 Representing instructions 3, Logical operatal operations 1
15:39
L6-6 Logical operations 2 , Decision making and branches 1
14:17
L6-7 Decision making and branches 2
14:57
L7-1 Review & procedure call (1)
15:38
L7-2 Procedure call (2)
15:21
L7-3 Procedure call (3)
14:13
L7-4 Non-leaf procedure call (1)
14:37
L7-5-1 Non-leaf procedure call(2)
08:14
L7-5-2 Communicating with people
15:49
L7-6 Addressing for 32-bit immediate and addresses (1)
10:52
L8-1 I-type branch instruction
25:00
L8-2 J-type instruction formate
22:58
L9-1 Translating and starting a program
20:12
L9-2 Arrays vs Pointer, ARM & MIPS ISA
29:59
L9-3 MIPS ALU-1
19:34
L9-4 MIPS ALU-2
15:05
L9-5 Overflow
08:46
L10-1 Ripple carry adder & carry look ahead adder
02:25
L10-2 Cascaded carry lookahead adder
01:15
L11-1 Multiplication-1: Unsigned multiplier
29:22
L11-2 Multiplication-2: Signed multiplier
18:02
L11-3 Multiplication-3: Booth's algorithm, Wallace Tree Multiplier
33:46
L12-1 Division
21:57
L12-2 Floating Point-1
10:31
L12-3 Floating Point-2
21:44
L13-1 Floating Point-3
27:28
L13-2 Floating-Point Addition
21:54
L14-1 Floating point multiplication & associativity
19:38
L14-2 Processor designing introduction(1)
11:23
L14-2 Processor designing introduction(2)
17:15
L14-3 Instruction set analysis
22:04
L14-4-1 Building datapath(1)
15:43
L14-4-2 Building datapath(2)
09:28
L15-1 Building the datapath (3)
21:18
L15-2 Single cycle processor and it's controls(1)
23:50
L16-1 Single cycle processor and it's controls(2)
27:13
L16-2 Single cycle processor and it's controls(3)
23:17
L17-1 Single cycle processor and it's controls(4)
06:27
L17-2 Overview of pipelining
12:57
L17-3 A pipelined data path(1)
22:03
L17-3 A pipelined data path(2)
10:08
L17-4 Pipelined control(1)
13:22
L17-4 Pipelined control(2)
15:02
L18-1 Data Hazards and forwardings-1
36:24
L18-2 Data hazards and forwarding -2
44:34
L19-1 Data Hazards and stalls
19:17
L20-1 Branch Prediction
37:21
L20-2 Hazard review (extra clip)
05:58
L20-2 Exceptions
27:47
L21-1 Superscalar and dynamic pipelining
29:58
L21-2 Static multiple issue
34:07
L21-3 Dynamic Multiple Issue, Register Renaming
16:14
L22-1 Memory hierarchy
41:21
L22-2 The basics of caches -1
21:01
L22-3 The basics of caches -2
29:25
L23-1 The basics of caches -3 [Review]
21:51
L23-2 The basics of chaches -4
26:03
L23-3 The basics of caches -5
18:07
L24-1 Measuring and improving cache performance
31:41
L24-2 Associative cache example
22:28
L24-3 Associativity, Multilevel cache
25:02
L24-4 Multilevel cache
15:19
L24-5 Virtual memory
25:12
L25-1-1 Virtual memory - basic
22:31
L25-1-2 Virtual memory - paging
23:08
L25-1-3 Virtual memory - translation
03:08
L25-2-1 Virtual memory - handling huge page table 1
08:35
L25-2-2Virtual memory - handling huge page table 2
14:27
L25-2-3 Virtual memory - TLB and cache 1
24:13
L25-2-4 Virtual memory - TLB and cache 2
24:41
L25-2-5 Virtual memory
05:11
L26-1-1 Framework of hierachy
16:19
L26-1-2 FSM to control a simple cache 1
04:43
L26-1-3 FSM to control a simple cache 2
10:50
L26-2 Parallelism and memory hierarchiy
20:12

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