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ESWEEK 2022 Trailers

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2022-10-05 11:21:33

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https://www.youtube.com/watch?v=tpnz06_8fBQ&list=PLMohsHZ1UrxteHzUvEegi4rQUFn830 https://www.youtube.com/watch?v=tpnz06_8fBQ&list=PLMohsHZ1UrxteHzUvEegi4rQUFn830Opx

eogyg14631 发消息

Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget

01:01

Detecting Spoofed Speeches via Segment-based Word CQCC and Average ZCR for Embed

00:53

A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heat

01:01

A Resource-Aware Optimization Model for Real-Time Systems Analysis and Design

01:01

Accuracy-Area Efficient Online Fault Detection for Robust Neural Network Softwar

01:00

Adaptive Edge Offloading Under Rate Limits- A Reinforcement Learning Approach

01:01

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

01:15

Adaptive Switch on Wear Leveling for Enhancing I_O Latency and Lifetime of High-

00:34

Agile and Sustainable Methodology for Designing Efficient Accelerators

01:02

Amphis- Managing Reconfigurable Processor Architectures with Generative Adversar

01:00

An Efficient BCNN deployment Method using Quality-aware Approximate Computing

00:52

An I_O Virtualization Framework with I_O-Related Memory Contention Control for R

01:01

An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks

00:59

Architecting Decentralization and Customizability in DNN Accelerators for Hardwa

00:59

ARMISTICE_ Micro-Architectural Leakage Modelling for Masked Software Formal Veri

01:17

Bits Ensemble_ Towards Light-Weight Robust Deep Ensemble by Bits Sharing

01:18

BLAST_ Belling the Black-Hat High-level Synthesis Tool

00:43

CapOS_ Capacitor Error Resilience for Energy Harvesting Systems

01:57

CASPHAr_ Cache-Managed Accelerator Staging and Pipelining in Heterogeneous Syste

01:00

Characterising the Effect of Deadline Misses on Time-Triggered Task Chains

01:00

CMQ- Crossbar-aware Neural Network Mixed-precision Quantization via Differentiab

00:56

Combating Stealthy Thermal Covert Channel Attack with its Thermal Signal Transmi

00:55

Cut and Forward_ Safe and Secure Communication for FPGA System on Chips

01:04

Design Automation for Microfluidic Biochips

00:50

Differentiable Inference of Temporal Logic Formulas

01:00

DynLiB_ Maximizing the Energy Availability of Hybrid Li-ion Battery Systems

01:09

Efficient Backward Reachability using the Minkowski Difference of Constrained Zo

01:02

Efficient Complete Verification of Neural Networks via Layer-wised Splitting and

01:00

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural

00:52

Enabling Weakly-Supervised Temporal Action Localization from On-Device Learning

01:34

Energy-efficient DNN Inference on Approximate Accelerators Through Formal Proper

01:00

Enhancing the Reliability and Security_ A Configurable Poisoning PUF against Mod

01:01

eRDAC- Efficient and Reliable Remote Direct Access and Control for Embedded Syst

01:18

Exploring Synchronous Page Fault Handling

01:01

Fast and Low Overhead Metadata Operations for NVM-based File System Using Slotte

00:57

Exploring Bitslicing Architectures for Enabling FHE-assisted Machine Learning

01:30

FLAM-PUF_ A Response Feedback-based Lightweight Anti-Machine Learning-Attack PUF

02:25

Formal Verification of Resource Synchronization Protocol Implementations_ A Case

00:57

FRL- Fast and Reconfigurable Accelerator for Distributed Sound Source Localizati

01:02

GCIM- Towards Efficient Processing of Graph Convolutional Networks in 3D-Stacked

01:19

GNN4REL_ Graph Neural Networks for Predicting Circuit Reliability Degradation

01:01

Hardware-Friendly Delayed Feedback Reservoir for Multivariate Time Series Classi

00:58

HARM- a Hint-based Assertion Miner

00:50

Horae_ A Hybrid I_O Request Scheduling Technique for Near-Data Processing based

00:57

Hybrid RRAM_SRAM In-Memory Computing for Robust DNN Acceleration

00:49

Industrial Paper_ Challenges in Rebooting Autonomy with Deep Learned Perception

01:01

Industry Paper_ System-Level Logical Execution Time for Automotive Software Deve

01:01

Industry Paper_ Towards Agile Design of Neural Processing Unit

00:58

Intermittent-aware Distributed Concurrency Control

01:01

iNVMFS_ An Efficient File System for NVRAM-Based Intermittent Computing Devices

00:53

LLSM_ A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash Memory

01:04

MAID-Q- Minimizing Tail Latency in Embedded Flash with SMR Disk via Q-learning M

01:07

Memory-computing Decoupling_ a DNN Multitasking Accelerator with Adaptive Data A

01:00

Mercury_ Instruction Pipeline Aware Code Generation for Simulink Models

00:59

Midas_ Safeguarding IoT Devices Against Malware via Real-Time Behavior Auditing

01:01

NASA_ NVM-Assisted Secure Deletion for Flash Memory

01:01

Near-Optimal Energy Management for Energy Harvesting IoT Devices using Imitation

01:08

NeuroMap_ Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Man

00:58

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectu

00:50

Online Re-routing and Re-scheduling of Time-Triggered Flows for Fault Tolerance

01:04

Optimizing Random Forest Based Inference on RISC-V MCUs at the Extreme Edge

00:53

PervasiveFL_ Pervasive Federated Learning for Heterogeneous IoT Systems

01:00

Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-

01:03

Provable and Guided State Space Exploration of Neural Network Control Systems us

01:15

PVoT- Reconfigurable Photovoltaic Array for Indoor Light Energy-powered Batteryl

01:32

Quantifying Information Leakage for Security Verification of Compiler Optimizati

01:01

ReaDy_ A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolut

01:05

Response-Time Analysis of Limited-Preemptive Sporadic DAG Tasks

01:00

Safety Analysis of Embedded Controllers Under Implementation Platform Timing Unc

01:01

SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Ne

01:01

Secured Data Transmission over Insecure Network-on-Chip by Modulating Inter-pack

00:49

SENTunnel_ Fast Path for Sensor Data Access on Automotive Embedded Systems

01:01

Sparsity-Aware Intelligent Spatiotemporal Data Sensing for Energy Harvesting IoT

01:01

Stateful Neural Networks for Intermittent Systems

01:01

Stochastic Guarantees for Adaptive Energy Harvesting Systems

01:06

STT-RAM-based In-Memory Computing Across the Memory Hierarchy

00:47

SWAP_ A Server-scale Communication-aware Chiplet-based Manycore PIM Accelerator

01:04

Tardis_ Embedded Operating System Fuzz Testing with Coverage Guidance

01:00

Throughput Maximization in Wireless Communication Systems Powered by Hybrid Ener

01:01

Tinkertoy_ Build your own operating systems for IoT devices

01:01

Stochastic Bit-Stream Processing Systems with New Perspectives Towards Vision an

01:01

Towards Event-Driven Context_ Javascript an Energy-Efficient Language for the In

00:58

Towards Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algor

01:01

Towards Register Spilling Security using LLVM and ARM Pointer Authentication

00:59

Verified Train Controllers for the Federal Railroad Administration Model- Balanc

01:01

Verifying Controllers with Vision-Based Perception using Safe Approximate Abstra

01:01

ViA- A Novel Vision-Transformer Accelerator Based on FPGA

01:04

Vulnerability Detection of ICS Protocols Via Cross-State Fuzzing

01:00

WA-OPShare_ Workload-adaptive Over-provisioning Space Allocation for Multi-tenan

01:01

When B+-tree Meets Skyrmion Memory_ How Skyrmion Memory Affects an Indexing Sche

01:00

Work in Progress_ Dynamic Offloading of Soft Real-time Tasks in SDN-based Fog Co

00:40

Work-in-Progress- BloCirNN- An Efficient Software_hardware Codesign Approach for

00:52

Work-in-Progress- Comparative Performance Evaluation of Thermal Covert Channel A

00:54

Work-in-Progress- Cooperative MLP-Mixer Networks Inference On Heterogeneous Edge

00:58

Work-in-Progress- SuperNAS- Fast Multi-Objective SuperNet Architecture Search fo

00:57

Work-in-Progress_ A Browser-Driven Sensor Service for Embedded IoT

01:10

Work-in-Progress_ A Processing-in-Pixel Accelerator based on Multi-level HfOx Re

01:01

Work-in-Progress_ ACAC_ An Adaptive Congestion-aware Approximate Communication M

00:56

Work-in-Progress_ Boot Sequence Integrity Verification with Power Analysis

00:52

Work-in-Progress_ CAMiSE_ Content Addressable Memory-integrated Searchable Encry

00:37

Work-in-Progress_ DRAM-MaUT_- DRAM Address Mapping Unveiling Tool for ARM Device

01:02

Work-in-Progress_ Efficient Low-latency In-Memory Addition

00:52

Work-in-Progress_ Emulation of biological tissues on an FPGA

01:00

Work-in-Progress_ ExpCache_ Online-Learning based Cache Replacement Policy for N

01:06

Work-in-Progress_ HeteroRW_ A Generalized and Efficient Framework for Random Wal

00:51

Work-in-Progress_ High-Performance Systolic Hardware Accelerator for RBLWE-based

01:01

Work-in-Progress_ High-Precision Short-Term Lifetime Prediction in TLC 3D NAND F

01:01

Work-in-Progress_ High-Precision Short-Term Lifetime Prediction in TLC 3D NAND F

00:37

Work-in-Progress_ Imprecise Computing with Hot-patching Technique for Computing

00:58

Work-in-Progress_ Lark_ A Learned Secondary Index Toward LSM-tree for Resource-C

01:01

Work-in-Progress_ MLGOPerf_ An ML Guided Inliner to Optimize Performance

00:59

Work-in-Progress_ NoRF_ A Case Against Register File Operands in Tightly-Coupled

00:59

Work-in-Progress_ Object Detection Acceleration Method by Improving Execution Ef

01:01

Work-in-Progress_ Reliability Evaluation of Power SCADA System with Three-Layer

00:50

Work-in-Progress_ RISC-V Based Low-cost Embedded Trace Processing System

01:05

Work-in-Progress_ Scheduler for Collaborated FPGA-GPU-CPU Based on Intermediate

01:00

Work-in-Progress_ Smart data reduction in SLAM methods for embedded systems

01:04

Work-in-Progress_ Toward a Robust, Reconfigurable Hardware Accelerator for Tree-

00:33

Work-in-Progress_ Toward Energy-efficient Using Near STT-MRAM Processing Archite

01:01

Work-in-Progress_ Towards a Theory of Robust Quantitative Semantics for Signal T

01:01

Work-in-Progress_ Ultra-fast yet Accurate Performance Prediction for Deep Neural

01:05

Work-in-Progress_ Utilizing Latency and Accuracy Predictors for Eﬀicient Hardwar

00:58

Work-in-Progress_ What to Expect of Early Training Statistics_ An Investigation

00:48

A Flexible Yet Efficient DNN Pruning Approach for Crossbar-based Processing-In-M

01:01

A High-Level Synthesis Approach for Precisely-Timed, Energy-Efficient Embedded S

01:00

Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet

00:33

Cyber-Physical Verification of Intermittently Powered Embedded System

00:58

Online Reset for Signal Temporal Logic Monitoring

00:54

Work-in-Progress Accelerated Matrix Factorization by Approximate Computing for R

00:35

SuperGuard The Solution for Using C standard Libraries in Safety-Critical Applic

01:04

Work-in-Progress- Towards a Smaller than Grain Stream Cipher-Optimized FPGA

01:08

An Open-Source Platform for Design and Programming of Partially Reconfigurable

00:45

Work-in-Progress Prediction-based Fine-Grained LDPC Reading to Enhance

01:04

CaPUF Cascaded PUF Structure for Machine Learning Resiliency

00:59

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