冷知识：ESP32有双核

The ESP32-S3 is a high-performance, low-power AIoT SoC integrating 2.4 GHz Wi-Fi and Bluetooth 5 (LE), built around a dual-core Xtensa® LX7 CPU running up to 240 MHz. It features a Harvard architecture with separate instruction and data buses, enabling simultaneous fetch and data access for improved throughput.

Core & Memory It includes 384 KB ROM, 512 KB SRAM, and 16 KB RTC memory (8 KB fast, 8 KB slow). External memory support extends to 1 GB Octal SPI Flash and 1 GB PSRAM, accessed via configurable I/D cache (ICache: 16–32 KB, DCache: 32–64 KB). The cache system uses an arbiter to manage dual-core simultaneous access.

AI Acceleration Vector instructions accelerate neural network and DSP workloads, supported by ESP-DSP and ESP-NN libraries. This enables efficient image recognition, voice wake-up, and other AI tasks directly on-device.

Peripherals & Interfaces The chip offers 45 programmable GPIOs with IO MUX and GPIO matrix for flexible pin mapping. Interfaces include SPI, I²C, I²S, UART, PWM, RMT, ADC, SD/MMC, TWAI, and USB OTG. Fourteen GPIOs support capacitive touch sensing. A GDMA controller with 5 TX and 5 RX channels offloads high-speed data transfers for peripherals like SPI, I²S, LCD/CAM, and cryptographic engines.

Connectivity Wi-Fi supports 802.11 b/g/n with 20/40 MHz bandwidth, while BLE 5.0 supports Coded PHY for long range and 2 Mbps PHY for high throughput. Both subsystems maintain stable RF performance even at high temperatures.

Security Hardware security includes AES-XTS flash encryption, RSA secure boot, digital signatures, HMAC, and a World Controller for trusted execution and privilege separation.

Power Management An Ultra-Low-Power (ULP) coprocessor enables deep sleep modes with RTC memory retention, making it ideal for battery-powered IoT devices.

Boot & Interrupt System The boot process involves a ROM-based first-stage loader, a configurable second-stage bootloader (partition table, OTA, encryption), and FreeRTOS-based application startup. A flexible interrupt matrix maps 99 interrupt sources to CPU0/CPU1 external interrupts.

This architecture makes the ESP32-S3 suitable for AIoT, wearables, smart home, and edge AI applications, balancing performance, connectivity, and security.