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Synopsys Design Compiler DC综合教程

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2021-09-28 15:37:03

https://www.youtube.com/watch?v=O0A7TKjnfAQ&list=PL40HX6x4OOCVbQzZc8gewPCpAaMpB_PCK

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Synopsys Design Compiler DC综合教程

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01. Basic Static Timing Analysis Timing Concepts Intro to Timing Libraries

20:13

02. Basic Static Timing Analysis Timing Concepts - Cell Delay

08:56

03. Basic Static Timing Analysis Timing Concepts - Net Delay

13:07

04. Basic Static Timing Analysis Timing Concepts - Clocks

20:37

05. Basic Static Timing Analysis Timing Checks

22:03

06. Basic Static Timing Analysis Timing Concepts - Timing Paths

15:18

07. Basic Static Timing Analysis Timing Constraints

06:19

08. Basic Static Timing Analysis Setting Timing Constraints

50:45

09. Basic Static Timing Analysis Analyzing Timing Reports

16:28

10. Static Timing Analysis(STA) of Digital circuits- Part 1 Combinational circui

11:46

11. Static Timing Analysis(STA) of Digital circuits- Part 2 Sequential circuits

11:07

12. What is a Clock in an FPGA

18:58

13. Setup, Hold, Propagation Delay, Timing Errors, Metastability in FPGA

11:08

14. Crossing Clock Domains in an FPGA

16:38

15. DVD - Lecture 5 Timing (STA)

02:01:33

16. Timing Analyzer Introduction to Timing Analysis

15:50

17. Best Design Practices for Timing Closure

50:44

18. Advanced Timing Exceptions False Path, Min Max Delay and Set Case Analysis

08:30

19. ⨘ } VLSI } 15 } Static Timing Analysis (STA) concepts, timing paths, and how

51:16

21. ⨘ } VLSI } 4 } Clock Domain Crossing (CDC) Techniques }

26:24

22. ⨘ } VLSI } 9 } Clock Domain Crossing (CDC) } FIFO }

19:42

23. ⨘ } VLSI } 10 } Clock Domain Crossing (CDC) } Reset Domain Crossing (RDC) }

14:45

24. ⨘ } VLSI } 11 } Clock Domain Crossing (CDC) } Multi Voltage Domains }

14:11

25. ⨘ } VLSI } 12 } Metastability }

31:29

26. ⨘ } VLSI } 18 } Clock Domain Crossing } Questa CDC Mentor 0-in }

33:27

27. Time Closure (Part 1)

34:49

28. Time Closure (Part 2)

35:05

29. Time Closure (Part 3)

31:07

30. Time Closure (Part 4)

30:30

31. Time Closure (Part 5)

32:58

33. Interview Question on Static Timing Analysis Re-timing Register Duplicat

03:26

Electronics Interview Questions- STA part 1

11:30

32. Electronics Interview Questions STA Part2 Hold Time Equation Hold Time Vio

03:30

35. Electronics Interview Questions STA Part 3 Combination logic duplication

07:46

34. Multicycle paths Explained with example

09:24

36. What is Static Timing Analysis Learn @ Udemy- VLSI Academy

02:36

37. How to do STA Introduction To Slack And Hold Timing Analysis Learn @ Udemy-

09:52

38. How to do Set-up and Hold Timing analysis Open to Innovate !!

10:10

39. What is Data Arrival And Required Time Learn @ Udemy- VLSI Academy

01:14

40. Introduction to data and latch timing

07:51

41. How to do STA Hold Timing Analysis Learn @ Udemy- VLSI Academy

04:54

42. Input delay constraints for interface setup hold analysis

08:43

43. VLSI Academy - L22 IntroductionToTimingWindow

01:13

44. VLSI Academy - L28 SetupTimingAnalysisRealClocks

00:59

45. VLSI Academy - L31 HoldTimingWithRealClocks

01:08

46. VLSI Academy-L35_Intro_To_Delay_Tables

01:17

47. VLSI Academy-L40_OR_AND_simultaneous_clock_gating_technique

01:17

48. VLSI Academy-L41_NAND_gates_as_clock_gating_cells

01:10

49. VLSI Academy- L45_Setup_Timing_Degrade_by_unbalanced_Skew

01:17

50. VLSI Academy-L46_Hold_Timing_Analysis_Real_Clocks

01:28

51. How to do Setup timing Analysis Real Clocks Learn @ Udemy- VLSI Academy

01:39

52. How to do Static Timing Analysis with Multiple Clocks Learn @ Udemy- VLSI Ac

09:48

53. How to do STA Setup Timing Analysis With Jitter And Real Clocks Learn @ Udem

08:33

54. How is Hold Timing Degrade by unbalanced Skew Learn @ Udemy- VLSI Academy

01:08

55. How to do Hold Timing Analysis After Pessimism Removal Learn @ Udemy- VLSI A

08:41

56. How to Generate Clock Definition Using Master Clock Edges Learn @ Udemy- VLS

09:46

57. What is the Generated Clock Definition Using Shifted Edge Learn @ Udemy- VLS

07:24

58. How reset synchronizers resolves reset deassertion

11:13

59. How to do OCV_TIMING Setup Time Graphical To Textual Conversion with example

09:03

60. How to do the OCV_TIMING OCV Based Setup Timing Analysis Learn @ Udemy- VLSI

09:08

61. How to do OCV_TIMING Setup Timing Analysis After Pessimism Removal Learn @ U

08:50

62. How to do OCV_TIMING Hold Timing Graphical To Textual Conversion Learn @ Ude

09:07

63. Conclusion Static timing Analysis

02:01

64. VLSI Academy- Static Timing Analysis - II

03:13

65. Digital Logic - Propagation Delay, Setup, and Hold times

04:58

66. Timing Analysis & Critical Paths

32:00

67. Introduction to Timing Analysis

01:12:07

68. Static Timing Analysis -Addition of Buffer (Part of Online Course)

10:45

69. STA_L1d - Importance of Timing From RTL to Logic Synthesis

14:36

70. STA_L1e -Timing Optimization During Logic Synthesis

11:19

71. STA_L1f - Overview of Floorplan Aware Synthesis

09:14

72. STA_L1g - Timing Check Overview in PD Flow

05:29

73. STA_L1h - STA Tool & Flow at different stages

04:55

74. CLK_L3 -Importance of Clock Skew in Timing Analysis (Part 1)

12:24

75. sec 3-03 Timing Analysis

13:19

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